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MC74VHC08 Quad 2-Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2-input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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14 SOIC-14 D SUFFIX CASE 751A 1 VHC08G AWLYWW
* * * * * * * * * * * *
High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 24 FETs or 6 Equivalent Gates Pb-Free Packages are Available*
A1 B1 A2 B2 A3 B3 A4 B4 1 2 4 5 9 10 12 13 3 Y1
14 TSSOP DT SUFFIX CASE 948G 1 VHC 08 ALYW G G
14 SOEIAJ-14 M SUFFIX CASE 965 1 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 74VHC08 ALYWG
6
Y2 Y = AB
8
Y3
(Note: Microdot may be in either location) 11 Y4
FUNCTION TABLE
Inputs Output B L H L H Y L L L H A L L H H
Figure 1. Logic Diagram
VCC 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8
ORDERING INFORMATION
1 A1 2 B1 3 4 5 6 Y2 7 GND
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
Y1 A2 B2 (Top View)
Figure 2. Pinout: 14-Lead Packages
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
November, 2005 - Rev. 6
Publication Order Number: MC74VHC08/D
MC74VHC08
III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIII I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIII I I II I I I II I I IIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIII IIIIIII II IIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII III I III I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I III I I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIII IIIIIIIIIIIIIIIIIIIIIII II II II I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage -0.5 to +7.0 -0.5 to +7.0 Vout IIK DC Output Voltage -0.5 to VCC +0.5 -20 20 25 50 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC TSSOP Package Packages 500 450 mW _C Tstg -65 to +150 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter DC Supply Voltage DC Input Voltage
Min 2.0 0 0
Max 5.5 5.5
Unit V V V
Vout TA
DC Output Voltage
VCC +85 100 20
Operating Temperature
-40 0 0
_C
tr, tf
Input Rise and Fall Time
VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL Parameter
Test Conditions
VCC V
TA = 25C Typ
TA = - 40 to 85C Min Max
Min
Max
Unit V V V
Minimum High-Level Input Voltage
2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5
1.50 VCC x 0.7
1.50 VCC x 0.7
Maximum Low-Level Input Voltage Minimum High-Level Output Voltage
0.50 VCC x 0.3
0.50 VCC x 0.3
VOH
Vin = VIH or VIL IOH = -50 mA
1.9 2.9 4.4
2.0 3.0 4.5
1.9 2.9 4.4
Vin = VIH or VIL IOH = -4.0 mA IOH = -8.0 mA Vin = VIH or VIL IOL = 50 mA
2.58 3.94
2.48 3.80
VOL
Maximum Low-Level Output Voltage
0.0 0.0 0.0
0.1 0.1 0.1
0.1 0.1 0.1
V
Vin = VIH or VIL IOL = 4.0 mA IOL = 8.0 mA Vin = 5.5 V or GND Vin = VCC or GND
0.36 0.36
0.44 0.44
Iin
Maximum Input Leakage Current Maximum Quiescent Supply Current
0 to 5.5 5.5
0.1 2.0
1.0 20.0
mA mA
ICC
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MC74VHC08
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III II III I I I I I IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II III II III I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I II III II III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol tPLH, tPHL Parameter TA = 25C Typ 6.2 8.7 4.3 5.8 4 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 Max 10.5 14.0 7.0 9.0 10 Test Conditions Min Max Unit ns Maximum Propagation Delay, A or B to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 8.8 12.3 5.9 7.9 10 Cin Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0 V 18 CPD Power Dissipation Capacitance (Note 1) pF 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Characteristic Typ 0.3 -0.3 Max 0.8 -0.8 3.5 1.5 Unit V V V V
VCC A or B 50% GND tPLH tPHL DEVICE UNDER TEST OUTPUT
TEST POINT
C L*
Y
50% VCC *Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
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MC74VHC08
ORDERING INFORMATION
Device MC74VHC08DR2 MC74VHC08DR2G MC74VHC08DTR2 MC74VHC08DTR2G MC74VHC08MEL MC74VHC08MELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) Shipping 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2500 Units / Tape & Reel 2000 Units / Tape & Reel 2000 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74VHC08
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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EEE CCC EEE CCC
MC74VHC08
PACKAGE DIMENSIONS
SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 0_ 10 _ 0.028 0.035 --- 0.056
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHC08/D

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